SR71040A architecture block diagram pc gen i-cache itlb bht decode register file dispatch buffer bru alu x alu y ld/st mov load math macc d- cache l2 cache dispatch fp reg file tb dtlb sysad s a n d c r aft t m s r 7 1 0 4 0 cac h eh i erarc h y primary instruction cache - ( l1) 16 kb, 16 byte line 2-way set associative line locking primary data cache - ( l1) 16 kb, 16 byte line 2-way set associative line locking write back, write through (write-allocate/no-write-allocate), bypass l2-l3 secondary unified cache - ( l2) 128kbonchip 4 -way set associative 32-byte line, line locking low power consumpt i on fully static design clock enabled registers for improved power management dynamic activation of sense amps. in caches high-performance system interface compatible with r4xxx/5xxx/7xxx sysad interface 133 mhz with split transactions and out-of-order return high-performance floating point fully mips64 compliant ieee - 754 compatible decoupled from integer pipeline extended features: 10 interrupts, 64 dual-entry tlb variable page sizes from 4 kbytes to 256 mbytes jtag interface compatible with ieee 1149.1 h i g h per f ormance arc h i tecture fully mips64 instruction set architecture (isa) compliant true 2-way superscalar architecture dual fetch, dual dispatch, up to 6-issue, up to 6-execute, dual-commit maximum operation rate of pipeline: 2 instructions per cycle out-of-order issue and dispatch in-order retires 9-stage pipeline for high clock frequency optimized pipeline bypass architecture for minimizing instruction interdependent stalls intelligent dynamic branch prediction bi-modal 3kbit table, branch predictor keeps pipeline full and minimizes branch mis-predict penalties speculative execution down predicted paths maximizes sustainable performance e n g i n e s f o r t h e d i g i t a t t l a g e t m SR71040A m i p s 6 4 s u p e r s c a l a r m i c r o p r o c e s s o r the SR71040A microprocessor comprises the following features: 600 to 800mhz two-way superscalar 9 stage pipeline with out of order executions and hardware branch prediction. primary instruction and data caches are both 16kb, and 2-way set associative on-chip secondary cache is 128kb and is 4-way set associative 133mhz sysad bus interface ieee 754 compatible floating point unit the SR71040A is available in two speed grades of 600mhz and 800mhz in a 256 pin tbga package. the SR71040A microprocessor is a mips64- tm tm compatible processor based on the proven 0.15u sr71010a design. the product provides a low cost, high-performance mips64-compatible processor to enable a new class of processor-based embedded systems, and also to provide an upgrade path for users of r4000- and r5000-class processors in low- to mid-range embedded systems. preliminary engines for the digital age tm ( datasheet : )
e n g i n e s f o r t h e d i g i t a t t l a g e t m contact us sandcraft, inc. 3003 bunker hill lane suite 101 santa clara, ca 95054 www.sandcraft.com phone: (408) 490-3200 fax: (408) 490-3111 email: sales @ s a n d c r a f t f f . c o m mips64tm is a trademark of mips copyright ? 2001 s a n d c r a f t f f s a n dcra ft tm s r 71 040 engines for the digital age tm tm sr71040 - 600-800 mhz core frequency 600mhz - 800 mhz instruction cache 16 kbyte (2 way) data cache 16 kbyte (2 way) l2 cache 128 kbyte (4 way) SR71040A-xxx-2t 256 tbga 600 - 800 mhz interface bus width (mips sysad) 64-bit interface bus frequency up to 133 mhz process 0.13um core vcc 1.2v i/o vcc 3.3v or 2.5v compilers: operating system: simulation tools: redhat (cygnus) wind river, linux sandcraft development tools sandcraft designator cpu speed package size development boards: sandcraft, marvell preliminary SR71040A mips64 superscalar microprocessor SR71040A-xxx-yy package type
|
